By Johan Huijsing, Michiel Steyaert, Arthur H.M. van Roermund
This 10th quantity of Analog Circuit layout concentrates on three subject matters: 1. Scalable Analog Circuits, 2. High-Speed D/A Converters, and three. RF energy Amplifiers. every one subject is roofed by way of 6 papers, written via the world over famous specialists on that subject. those papers have an educational nature geared toward enhancing the layout of analog circuits. The booklet is split into 3 components: half I, Scalable Analog Circuit layout describes in 6 papers problems with: scalable high-speed layout, scalable high-resolution mixed-mode ADC and OpAmp layout, scalable high-voltage layout for XDSL, scalability of wire-line entrance ends, reusable IP analog layout, and porting CAD analog layout. half II, High-Speed D/A Converters describes in 6 papers problems with: advent to high-speed D/A converter layout, retargetable 12-bit 200-MHz CMOS present steerage layout, high-speed CMOS D/A converters for upstream cable purposes, static and dynamic functionality boundaries, the linearity problem of D/A converters for communications, and a 400-MHz, 10-bit charge-domain CMOS D/A converter for low-spurious frequency synthesis. half III, RF strength Amplifiers describes in 6 papers problems with: procedure points, assessment and trade-offs, linear transmitter architectures, GaAs microwave SSPAs, Monolithic transformer-coupling in Si-bipolar, and RF strength amplifier layout in CMOS.
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Additional info for Analog Circuit Design: Scalable Analog Circuit Design, High-Speed D A Converters, RF Power Amplifiers
If a 3-bit DAC is made of 8 supposedly matched elements, if these elements are used in randomised combinations to create the 8 voltage levels then it is obvious that this maps non-linearity due to element mis-match into noise. As always the detail is more complex but work in this area is relatively well published [14-30]. 34 4. OPAMP ARCHITECTURES The A/D converters discussed above are very difficult to drive. The capacitor-based successive approximation converters typically sample the input voltage directly onto the array capacitance to form a simple inherent sample-and-hold action.
Architectures which meet these requirements have been discussed. 6. REFERENCES (successive approximation converters) 1) “A Two-Stage Weighted Capacitor Network for D/A-A/D Conversion” Yee, Terman and Heller, IEEE Jnl. of Solid State Circuits, Vol. 14, pp. 778-781, Aug. 1979 2) “A Low Power 12b Analog to Digital Converter with On-Chip Precision Trimming” de Wit et al. IEEE Jnl. of Solid State Circuits, Vol. 28, pp. 455-461, Apr. 1993 (self-calibration) 40 3) “A Self-Calibrating 15 bit CMOS A/D Converter” Lee, Hodges and Gray, IEEE Jnl.
3-V, 10-b, 25-MSample/s Two-Step ADC in CMOS", IEEE Journal of Solid-State Circuits (JSSC), Vol. 34, No. 12, December 1999, pp. 1803-1811.  Ploeg, Hendrik van der, et. 25um CMOS ADC in Technical Digest ISSCC, 2001, pp. 132–439. K. bob. com ABSTRACT This paper discusses architectures for analog to digital interchange which are suitable for implementation in deep sub-micron CMOS mixed mode technologies. Discussed in detail are successive approximation and low over-sampling ratio sigmadelta converters giving >12 bits resolution at order MHz bandwidth.